Evidence of Large Voids in Pure-Silica-Zeolite Low-k Dielectrics Synthesized by Spin-on of Nanoparticle Suspensions

The downscaling of feature sizes in integrated circuits (IC) requires on-chip interconnects with low dielectric constant layers (low-k) that mitigate the increase in propagation delay and power consumption. Several candidate low-k materials based on porous silicates have been proposed. Whereas porosity is beneficial for lowering the dielectric constant, it has detrimental effects on the mechanical properties of the layer, strongly complicating the integration process of the on-chip interconnects. In addition to a low dielectric constant and sufficient mechanical strength, the pores in dielectric layers need to be narrow (<5 nm) and uniform to permit a proper sealing that avoids electrical breakdowns resulting from diffusion of Cu and other conducting species. Dielectric layers that consist of pure-silica zeolite (PSZ) prepared by in situ crystallization seem to be outstanding, as they achieve high elastic moduli in combination with low k values and, moreover, pores are reported to be hardly 0.5 nm wide. High stiffness results from the crystalline nature of the zeolite. Silicalite-1 (i.e., PSZ with MFI framework topology) is a commonly investigated zeolite. By spin-on deposition of a suspension of Silicalite-1 nanocrystals together with residual silica from the synthesis, a layer with a bimodal pore size distribution (PSD) is obtained, comprising zeolite channels with diameters of ca. 0.5 nm and interstitial voids with diameters smaller than 4 nm located between the Silicalite-1 nanocrystals. This bimodal pore model has been adopted in several studies and reviews. With Silicalite-1,